AMD Announces Zen 4 Microarchitecture Under Development

Irving Hamilton
November 7, 2018

During its Next Horizon event, AMD has also taken the opportunity to release initial information regarding its upcoming datacenter-centric Epyc processors codenamed "Rome".

AMD did not stop there, but also show a live demo of prototype single socket AMD EPYC Rome, which has support for up to 4TB of DRAM and offers 128-lanes of PCIe 4.0, against Intel's "best-in-class" Skylake dual-socket platform with two Intel 8180M Platinum CPUs, with support for up to 3TB of DRAM and offering 96 PCIe 3.0 lanes.

This, AMD hopes, will ease the workload that both customers and server makers have to do to make the switch to the new silicon. The chips will be manufactured by TSMC on its leading 7nm node, which the company says will give it a significant advantage over Intel, which is now struggling with its own 10nm process. The CPU chips which are called chiplets by AMD are connected to the I/O die through an "enhanced version" of the company's Infinity Fabric interconnect link. AMD says this will greatly help with uniform memory access latency, which was potentially a bottleneck when data had to hop from one core complex to another. The GPU, meanwhile, is claimed to be the world's fastest double-precision accelerator, with the MI60 incarnation offering 7.4 teraflops of peak 64-bit floating point performance and the MI50 up to 6.7 teraflops. Security is also improved, with full support for data encryption as it passes from CPU to memory.

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AMD is now sampling EPYC "Rome" chips with customers, with the chips expected to launch sometime in 2019. The Zen 4 is currently in development, so the company does not share many details about it right now.

AMD was also focused on providing a stable roadmap revealing that Zen 2 EPYC Rome is sampling now, with availability expected in 2019, while Zen 3 Milan is on track and should come sometime in 2020. Working under the codename Rome, the chip is claimed to offer considerable improvements in instructions-per-clock (IPC), the addition of PCI Express 4.0 connectivity, and a claimed doubling of performance-per-socket for traditional compute and quadrupling for floating-point operations compared to current-generation Epyc chips while retaining socket compatibility.

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